Non-volatile solid-state memory is used in many electronic components, devices and systems to provide programmable data storage that is retained without the need for an external power source. One well-known type of non-volatile solid-state memory is based on floating gate device technology. A floating gate device is a type of metal-oxide-semiconductor field-effect transistor (MOSFET) that uses a conductive, but insulated floating gate, between a conventional control gate and the channel, to store charge. Another type of non-volatile solid-state memory is based on SONOS (silicon-oxide-nitride-oxide-silicon) devices. SONOS devices provide several advantages over conventional floating-gate memories, including immunity from single point failures and programming at lower voltages. In contrast to floating-gate devices, which store charge on a conductive floating gate, SONOS devices trap charge in a dielectric layer. SONOS transistors are programmed and erased using a quantum mechanical effect known as uniform channel modified Fowler-Nordheim tunneling. This method of programming and erase is known in the art to provide better reliability than other methods of charge storage such as hot carrier injection. A SONOS transistor is a type of MOSFET with a charge-trapping dielectric stack (ONO stack) between a conventional control gate and a channel in the body of the transistor. A SONOS transistor can be fabricated as a P-type or N-type MOSFET using CMOS (complementary metal-oxide-semiconductor) fabrications methods
A SONOS transistor can be programmed or erased by applying a voltage of the proper polarity, magnitude and duration between the control gate and the channel of the device. A positive gate-to-channel voltage causes electrons to tunnel from the channel through an oxide layer (tunnel oxide) to a charge-trapping dielectric layer and a negative gate-to-channel voltage causes holes to tunnel from the channel through the tunnel oxide to the charge-trapping dielectric layer. The trapped charge modulates the threshold voltage of the device. In one case, the threshold voltage of the transistor is raised and in the other case the threshold voltage of the transistor is lowered. The threshold voltage is the gate-to-source voltage that causes the transistor to conduct current between drain and source when a voltage is applied between the drain and source terminals.
Typically, a SONOS transistor is used to store one bit of information, either a logical “0” or a logical “1,” associated with a uniform trapped-charge density corresponding to the programmed and erased states (the choice of which state corresponds to which logic level is arbitrary). The state of the transistor is read by applying a gate voltage with a value that is between the erased threshold voltage and the programmed threshold voltage and sensing the current that flows between the drain and source under an applied drain-to-source voltage. In one state the transistor conducts current and in the other state the transistor does not conduct current.
The quality of a SONOS memory device is measured by its endurance and data retention. Endurance is the number of program/erase cycles (e.g., 1 million) that a device can undergo while maintaining a specified separation (memory window) between the programmed threshold voltage and the erased threshold voltage. Data retention is the period of time following endurance cycling that a device maintains another specified memory window. A large memory window reduces data errors when reading the device.
In order to increase data storage densities, two-bit SONOS devices have been designed and fabricated that rely on the non-conductive characteristics of the charge-trapping dielectric layer. In these devices, the type and density of the trapped charge is controlled independently at the edges of the device. FIG. 1A illustrates a simplified cross-section (not to scale) of a conventional N-type SONOS device. The SONOS device is fabricated on a diffused P-well in an N-type substrate. Two N+ source/drain diffusions provide ohmic contacts and define a channel region. A tunnel oxide layer is grown above the channel, followed by the trapping oxide layer, a blocking oxide layer and a control gate. A P+ diffusion in the P-well provides an ohmic contact for bulk programming and erase operations.
FIG. 1B illustrates how a conventional SONOS device can be used to provide 2-bit programming functionality. In FIG. 1B, a negative voltage is applied between one source/drain contact on the left and the control gate, and a positive voltage is applied between the other source/drain contact on the right and the control gate. The negative voltage creates an electric field that causes electrons to tunnel from the channel, through the tunnel oxide, to the trapping oxide layer. The positive voltage creates an electric field that causes electrons to tunnel from the trapping oxide layer, through the tunnel oxide layer, to the channel (the tunneling of electrons in one direction is equivalent to the tunneling of holes in the opposite direction). The amount of charge transport is greatest at the edges of the tunnel oxide layer where the electric field strength is greatest.
FIG. 1C illustrates the state of the SONOS device after the programming voltages are removed. The trapped electrons on the left side of the device repel electrons from the channel, depleting the channel and leaving a positive space charge. The trapped holes on the right side of the device attract electrons to the channel, which inverts the channel. In this state, the device has a positive threshold voltage on the left and a negative threshold voltage on the right. The positive and negative threshold voltages can be associated with a “1” and “0” respectively.
FIG. 2A illustrates the trapped charge density profile across the length (l) of the trapping oxide layer, corresponding to the “10” programmed state of the SONOS device in FIG. 1C. FIGS. 2B, 2C and 2D correspond to the other possible states of the device as a function of the selection of programming voltages. This approach to 2-bit SONOS programming works as long as the charge densities on opposite ends of the trapping layer can be independently controlled. At sufficiently small device geometries, however, this approach breaks down because the charges and programming voltages interact. FIGS. 3A through 3D illustrate the effect of a short channel geometry on conventional 2-bit SONOS programming.
FIG. 3A illustrates the charge profile of a short channel SONOS device programmed to a “00” state, where holes are trapped in both ends of the trapping oxide layer. In FIG. 3B, the right side of the device has been re-programmed to a “1” state by the application of a negative source-to-gate voltage that causes electrons to tunnel into the trapping oxide layer (the previous charge density profile is shown as a dotted line in FIG. 3B). However, as illustrated in FIG. 3B, the density of trapped holes on the left side of the device has also been depleted by the re-programming voltage on the right side. As a result, the magnitude of the threshold voltage on the left side of the device is reduced and the quality of the “0” is degraded.
FIGS. 3C and 3D illustrate the comparable effect when a short channel SONOS device is programmed to a “11” state and one side is re-programmed to a “0” state. In this case, the quality of the “1” on the other side of the device is degraded by a depletion of trapped electrons and a reduction in the magnitude of the threshold voltage on that side of the device.